A known type of data converter for performing A/D conversion with high resolution may be referred to as sigma delta modulation. A sigma delta converter having cascaded feedback loops is taught in U.S. Pat. No. 4,704,600 entitled "An Oversampling Converter" by Uchimura et al. Uchimura et al. have taught the use of a multi-stage converter which performs an integration of an analog input signal with feedback to move quantization error from the passband frequency range to higher frequencies. It is known that the cascading of sigma delta modulators provides high performance A/D conversion. Known oversampling converters, including the Uchimura converter, typically operate at a single predetermined high sampling frequency. A potentially troublesome portion of a sigma delta modulator is an analog integrator circuit which is used to implement the modulation. The analog integrator must be designed to fully settle or resolve an output at a high sampling frequency. Since the integrator is an analog circuit, a slow clock rate is desirable to allow the circuit as much time to settle as possible. However, if the sampling rate of the modulator is reduced to accomodate the need for a slow clock rate for the integrator, a significant increase in output quantization noise results. For example, in a double integration sigma delta converter an increase in noise of 15 dB per octave results as explained by James Candy in "A Use of Double Integration in Sigma Delta Modulation", IEEE Transactions on Communications, Vol. Com-33, No. 3, March 1985, pages 249-258. Therefore, the analog integrator must be a very high performance analog circuit to perform at high sampling frequencies required to achieve desired conversion performance.